ITR Collaborative Research: Programmable Graph Architecture for High Level Transformations of Multimedia Applications

Programmable Graph Architectures For High Level Transformations of Multimedia Applications Abstract In this research we will investigate transformational algorithms, architecture, and design of programmable graph architectures, to map high-level representations of multimedia operations directly into hardware. We expect that this spatial mapping will substantially increase the computational density of processor chips, especially for those computations that make extensive use of matrix operations. The computations on these programmable graph architectures will rely on transforms between matrix groups and Cayley graphs rather than traditional arithmetic and logic operations used by conventional microprocessors. In particular, we plan to: (i) establish an instruction set for programmable graph architectures that is computationally efficient for multimedia applications; (ii) provide efficient algorithms to transform these instructions to graph routing problems in Cayley graphs; and (iii) examine the optimization issues pertaining to the design parameters of Cayley graphs. We expect this investigation to lead to prototypes of next generation multimedia machine architectures that are likely to be significantly different from the conventional fine-grained microarchitectures of today. The design and development of efficient multimedia processor architectures is important due to the increasing role of multimedia in everyday applications.