20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

Timur V. Filippov; Anubhav Sahu; Alex F. Kirichenko; Igor V. Vernik; Mikhail Dorojevets; Christopher L. Ayala; Oleg A. Mukhanov

doi:10.1016/j.phpro.2012.06.130

20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

Timur V. Filippov
, Anubhav Sahu
, Alex F. Kirichenko
, Igor V. Vernik
, Mikhail Dorojevets
, Christopher L. Ayala
, Oleg A. Mukhanov

Electrical Engineering

HYPRES, Inc.
Stony Brook University

Research output: Contribution to journal › Conference article › peer-review

95 Scopus citations

Abstract

We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES' standard 4.5 kA/cm² process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and highspeed test results for the 8-bit ALU circuit.

Original language	English
Pages (from-to)	59-65
Number of pages	7
Journal	Physics Procedia
Volume	36
DOIs	https://doi.org/10.1016/j.phpro.2012.06.130
State	Published - 2012
Event	Superconductivity Centennial Conference, SCC 2011 - The Hague, Netherlands Duration: Sep 18 2011 → Sep 23 2011

Keywords

A lu
Datapath
Microprocessor
RSFQ

Access to Document

10.1016/j.phpro.2012.06.130

Cite this

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title = "20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit",

abstract = "We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES' standard 4.5 kA/cm2 process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and highspeed test results for the 8-bit ALU circuit.",

keywords = "A lu, Datapath, Microprocessor, RSFQ",

author = "Filippov, \{Timur V.\} and Anubhav Sahu and Kirichenko, \{Alex F.\} and Vernik, \{Igor V.\} and Mikhail Dorojevets and Ayala, \{Christopher L.\} and Mukhanov, \{Oleg A.\}",

note = "Publisher Copyright: {\textcopyright}2012 Published by Elsevier B.V. Selection and/or peer-review under responsibility of the Guest Editors.; Superconductivity Centennial Conference, SCC 2011 ; Conference date: 18-09-2011 Through 23-09-2011",

year = "2012",

doi = "10.1016/j.phpro.2012.06.130",

language = "English",

volume = "36",

pages = "59--65",

journal = "Physics Procedia",

issn = "1875-3884",

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T1 - 20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

AU - Filippov, Timur V.

AU - Sahu, Anubhav

AU - Kirichenko, Alex F.

AU - Vernik, Igor V.

AU - Dorojevets, Mikhail

AU - Ayala, Christopher L.

AU - Mukhanov, Oleg A.

PY - 2012

Y1 - 2012

N2 - We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES' standard 4.5 kA/cm2 process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and highspeed test results for the 8-bit ALU circuit.

AB - We have designed and tested at high frequency an RSFQ-based Arithmetic-Logic Unit (ALU), the critical component of an 8-bit RSFQ processor datapath. The ALU design is based on a Kogge-Stone adder and employs an asynchronous wave-pipelined approach scalable for wide datapath processors. The 8-bit ALU circuit was fabricated with HYPRES' standard 4.5 kA/cm2 process and consists of 7,950 Josephson junctions, including input and output interfaces. In this paper, we present chip design and highspeed test results for the 8-bit ALU circuit.

KW - A lu

KW - Datapath

KW - Microprocessor

KW - RSFQ

UR - https://www.scopus.com/pages/publications/84870792887

U2 - 10.1016/j.phpro.2012.06.130

DO - 10.1016/j.phpro.2012.06.130

M3 - Conference article

AN - SCOPUS:84870792887

SN - 1875-3884

VL - 36

SP - 59

EP - 65

JO - Physics Procedia

JF - Physics Procedia

T2 - Superconductivity Centennial Conference, SCC 2011

Y2 - 18 September 2011 through 23 September 2011

ER -

20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

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Keywords

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