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A 1.2GHz adaptive floating gate comparator with 13-bit resolution

  • University of Maryland, College Park

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations

Abstract

We present a high-speed voltage comparator that uses floating gate adaptation to achieve high comparison resolution. The comparator uses nonvolatile charge storage for either offset nulling or automatic programming of a desired offset. We exploit the negative feedback functionality of pFET hot-electron injection to achieve fully automatic offset cancellation. The design has been fabricated in a commercially available 0.35μm process. Experimental results confirm the ability to reduce the variance of the comparator offset 3600× and to accurately program a desired offset with maximum observed residue offset of 469μV and standard deviation 199μV. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1V to 1V. The comparator operates at 1.2GHz with a power consumption of 2.97mW.

Original languageEnglish
Article number1466043
Pages (from-to)6146-6149
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

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