A coarse-grained FPGA architecture for reconfigurable baseband modulator/demodulator

This paper proposes a coarse-grained FPGA architecture that serves as a core for a reconfigurable baseband modulator/demodulator. It can be configured as either an FFT processor or FIR filters with multiple correlators, a key module for supporting OFDM, DSSS and FHSS systems. It allows for different sizes of FFT and FIR and for different numbers of correlators. By incorporating variable rate multipliers the architecture can handle a wide range of data rates at minimal power dissipation. Our architecture is compared with those based on commercial FPGA, low-power DSP and other hybrid structures. We show that our approach can achieve better performance and lower power consumption for the targeted applications.