A fully differential CMOS capacitance sensor design, testing and array architecture

The paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances to rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the ±20 fF range, appropriate for sensing live cells using on-chip microelectrodes. The paper also proposes an array architecture based on a shielded current routing bus that allows for a single measurement circuit to be shared by all the sensor pixels without compromising performance. This eliminates the need for individual pixel calibration. Each sensor pixel comprises 6 minimum size digital transistors, enabling high density integration. The sensor employs a 3-phase clocking scheme that enables gain tuning and also limits output voltage offsets. The paper presents data obtained from 5 chips fabricated in a commercially available 2-poly, 3-metal, 0.5 μm CMOS technology, each of them comprising individual circuits measuring the substrate-coupling capacitances of metal3 electrodes of varying sizes. The test data indicates successful sensor operation with a maximum sensitivity of 126 mV/fF, a maximum achievable resolution of 14 aF and an output dynamic range of 69.4 dB.