A high-speed multi-port data buffer design for low-energy DSP applications

Area and power of data storage elements can be excessively large in many data intensive DSP ASICs, such as high-throughput pipelined FFTs and data interleavers. In this paper, we present a low-complexity multi-port data buffer design methodology based on dynamic memory configuration that results in small area and low power overhead by adapting the buffer architecture to their data access requirements. The buffer minimizes the number of transistors and simplifies the interface between memory core and external digital circuitry. The buffer can be designed with a low cost digital circuit processing technology. To evaluate our methodology, we designed buffer for data interleaver and pipelined FFT that require high throughput. We compare the buffer with conventional buffers based on static memory.