A Robust Matrix-Multiplication Array

P. J. Varman; I. V. Ramakrishnan; D. S. Fussell

doi:10.1109/TC.1984.1676353

A Robust Matrix-Multiplication Array

P. J. Varman
, I. V. Ramakrishnan
, D. S. Fussell

Computer Science

Rice University
University of Texas at Austin

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size. Multiplication of two n x n matrices requires 0(n) processors and has a time complexity of 0(n2) cycles.

Original language	English
Pages (from-to)	919-922
Number of pages	4
Journal	IEEE Transactions on Computers
Volume	C-33
Issue number	10
DOIs	https://doi.org/10.1109/TC.1984.1676353
State	Published - Oct 1984

Keywords

Array processor matrix multiplication reconfigurability robust VLSI wafer-scale integration

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10.1109/TC.1984.1676353

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A Robust Matrix-Multiplication Array

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Keywords

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