A Two-Step SAR Capacitance-to-Digital Converter

Alexander Castro; Pamela Abshire

doi:10.1109/MWSCAS57524.2023.10406025

A Two-Step SAR Capacitance-to-Digital Converter

Alexander Castro
, Pamela Abshire

Electrical Engineering

University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The design of a two-step successive approximation register (SAR) capacitance-to-digital converter (CDC) is presented. First the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. Repeated fine conversions occur until an out-of-range condition arises. These bits are communicated off chip on an I2C bus. The effective number of bits (ENOB) is compared for sinusoidally varying capacitance inputs. The circuit achieves 9 ENOB with a 28μs conversion time under nominal conditions and 8.2 ENOB with 14μ s conversion time when overclocked. This equates to an ENOB throughput of 321kbits/s and 585kbits/s, respectively.

Original language	English
Title of host publication	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	74-78
Number of pages	5
ISBN (Electronic)	9798350302103
DOIs	https://doi.org/10.1109/MWSCAS57524.2023.10406025
State	Published - 2023
Event	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 - Tempe, United States Duration: Aug 6 2023 → Aug 9 2023

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Conference

Conference	2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Country/Territory	United States
City	Tempe
Period	08/6/23 → 08/9/23

Keywords

Capacitance-to-digital converter (CDC)
offset compensation
successive approximation register (SAR)

Access to Document

10.1109/MWSCAS57524.2023.10406025

Cite this

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title = "A Two-Step SAR Capacitance-to-Digital Converter",

abstract = "The design of a two-step successive approximation register (SAR) capacitance-to-digital converter (CDC) is presented. First the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. Repeated fine conversions occur until an out-of-range condition arises. These bits are communicated off chip on an I2C bus. The effective number of bits (ENOB) is compared for sinusoidally varying capacitance inputs. The circuit achieves 9 ENOB with a 28μs conversion time under nominal conditions and 8.2 ENOB with 14μ s conversion time when overclocked. This equates to an ENOB throughput of 321kbits/s and 585kbits/s, respectively.",

keywords = "Capacitance-to-digital converter (CDC), offset compensation, successive approximation register (SAR)",

author = "Alexander Castro and Pamela Abshire",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023 ; Conference date: 06-08-2023 Through 09-08-2023",

year = "2023",

doi = "10.1109/MWSCAS57524.2023.10406025",

language = "English",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "74--78",

booktitle = "2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023",

}

Castro, A & Abshire, P 2023, A Two-Step SAR Capacitance-to-Digital Converter. in 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. Midwest Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 74-78, 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, United States, 08/6/23. https://doi.org/10.1109/MWSCAS57524.2023.10406025

A Two-Step SAR Capacitance-to-Digital Converter. / Castro, Alexander; Abshire, Pamela.
2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 74-78 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Two-Step SAR Capacitance-to-Digital Converter

AU - Castro, Alexander

AU - Abshire, Pamela

PY - 2023

Y1 - 2023

N2 - The design of a two-step successive approximation register (SAR) capacitance-to-digital converter (CDC) is presented. First the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. Repeated fine conversions occur until an out-of-range condition arises. These bits are communicated off chip on an I2C bus. The effective number of bits (ENOB) is compared for sinusoidally varying capacitance inputs. The circuit achieves 9 ENOB with a 28μs conversion time under nominal conditions and 8.2 ENOB with 14μ s conversion time when overclocked. This equates to an ENOB throughput of 321kbits/s and 585kbits/s, respectively.

AB - The design of a two-step successive approximation register (SAR) capacitance-to-digital converter (CDC) is presented. First the coarse conversion stage performs a capacitive offset compensation down to within 10fF. The fine conversion stage converts the amplified residue voltage with a resolution of 200aF. Repeated fine conversions occur until an out-of-range condition arises. These bits are communicated off chip on an I2C bus. The effective number of bits (ENOB) is compared for sinusoidally varying capacitance inputs. The circuit achieves 9 ENOB with a 28μs conversion time under nominal conditions and 8.2 ENOB with 14μ s conversion time when overclocked. This equates to an ENOB throughput of 321kbits/s and 585kbits/s, respectively.

KW - Capacitance-to-digital converter (CDC)

KW - offset compensation

KW - successive approximation register (SAR)

UR - https://www.scopus.com/pages/publications/85185386197

U2 - 10.1109/MWSCAS57524.2023.10406025

DO - 10.1109/MWSCAS57524.2023.10406025

M3 - Conference contribution

AN - SCOPUS:85185386197

T3 - Midwest Symposium on Circuits and Systems

SP - 74

EP - 78

BT - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

Y2 - 6 August 2023 through 9 August 2023

ER -

A Two-Step SAR Capacitance-to-Digital Converter

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Keywords

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