Algorithmic modification of Particle Filters for hardware implementation

Particle filters are sequential Monte Carlo methods that have recently gained popularity in solving various problems in communications and signal processing. These filters have been shown to outperform traditional filters in important practical scenarios. However, they are computationally intensive and hence development of hardware for their real time implementation is an important and challenging research issue. In this paper we present some novel modifications applied to two particle filtering algorithms viz. Sampling Importance Resampling Filters (SIRFs) and Gaussian Particle Filters (GPFs) to make these filters suitable for implementation. We evaluate the proposed algorithms with respect to potential throughput and hardware resources. These modifications allow implementation of parallel architectures for these filters. Architectural parameters of proposed architectures for these filters are evaluated and compared.