An optimized gate-loop layout for multi-chip SiC MOSFET power modules

Miao Wang; Fang Luo; Longya Xu

doi:10.1109/WiPDA.2015.7369279

An optimized gate-loop layout for multi-chip SiC MOSFET power modules

Miao Wang
, Fang Luo
, Longya Xu

Electrical Engineering

Ohio State University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching loss can be reduced with a "reverse matching arrangement" between the gate loop and the power loop. Specifically, to assign a short gate loop to the device that has a large power-loop inductance, and vice versa. In addition, shared traces from the gate driver to the paralleled devices could further reduce the total switching loss.

Original language	English
Title of host publication	WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	215-219
Number of pages	5
ISBN (Electronic)	9781467378857
DOIs	https://doi.org/10.1109/WiPDA.2015.7369279
State	Published - Dec 30 2015
Event	3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2015 - Blacksburg, United States Duration: Nov 2 2015 → Nov 4 2015

Publication series

Name	WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications

Conference

Conference	3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2015
Country/Territory	United States
City	Blacksburg
Period	11/2/15 → 11/4/15

Keywords

gate-loop layout
multi-chip power module
SiC metal-oxide-semiconductor field-effect-transistor
switching loss

Access to Document

10.1109/WiPDA.2015.7369279

Cite this

Wang, M., Luo, F., & Xu, L. (2015). An optimized gate-loop layout for multi-chip SiC MOSFET power modules. In WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications (pp. 215-219). Article 7369279 (WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WiPDA.2015.7369279

@inproceedings{123e6d334bcb4e0997e070f5d4768e36,

title = "An optimized gate-loop layout for multi-chip SiC MOSFET power modules",

abstract = "This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2\% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching loss can be reduced with a {"}reverse matching arrangement{"} between the gate loop and the power loop. Specifically, to assign a short gate loop to the device that has a large power-loop inductance, and vice versa. In addition, shared traces from the gate driver to the paralleled devices could further reduce the total switching loss.",

keywords = "gate-loop layout, multi-chip power module, SiC metal-oxide-semiconductor field-effect-transistor, switching loss",

author = "Miao Wang and Fang Luo and Longya Xu",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2015 ; Conference date: 02-11-2015 Through 04-11-2015",

year = "2015",

month = dec,

day = "30",

doi = "10.1109/WiPDA.2015.7369279",

language = "English",

series = "WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications",

}

Wang, M, Luo, F & Xu, L 2015, An optimized gate-loop layout for multi-chip SiC MOSFET power modules. in WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications., 7369279, WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, Institute of Electrical and Electronics Engineers Inc., pp. 215-219, 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2015, Blacksburg, United States, 11/2/15. https://doi.org/10.1109/WiPDA.2015.7369279

An optimized gate-loop layout for multi-chip SiC MOSFET power modules. / Wang, Miao; Luo, Fang; Xu, Longya.
WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications. Institute of Electrical and Electronics Engineers Inc., 2015. p. 215-219 7369279 (WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An optimized gate-loop layout for multi-chip SiC MOSFET power modules

AU - Wang, Miao

AU - Luo, Fang

AU - Xu, Longya

PY - 2015/12/30

Y1 - 2015/12/30

N2 - This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching loss can be reduced with a "reverse matching arrangement" between the gate loop and the power loop. Specifically, to assign a short gate loop to the device that has a large power-loop inductance, and vice versa. In addition, shared traces from the gate driver to the paralleled devices could further reduce the total switching loss.

AB - This paper investigates the impact of gate-loop layouts on the switching loss of a multi-chip silicon carbide metal-oxide-semiconductor field-effect-transistor (MSOFET) power module. Six gate loop layouts are proposed and evaluated in switching simulations. A 16.2% difference on the total switching loss is observed between a good and a bad gate loop layout. The results shows that the total switching loss can be reduced with a "reverse matching arrangement" between the gate loop and the power loop. Specifically, to assign a short gate loop to the device that has a large power-loop inductance, and vice versa. In addition, shared traces from the gate driver to the paralleled devices could further reduce the total switching loss.

KW - gate-loop layout

KW - multi-chip power module

KW - SiC metal-oxide-semiconductor field-effect-transistor

KW - switching loss

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M3 - Conference contribution

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BT - WiPDA 2015 - 3rd IEEE Workshop on Wide Bandgap Power Devices and Applications

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ER -

An optimized gate-loop layout for multi-chip SiC MOSFET power modules

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Keywords

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