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Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps

  • Carnegie Mellon University
  • Intel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.

Original languageEnglish
Title of host publicationISTFA 2003
Subtitle of host publicationConference Proceedings from the 29th International Symposium for Testing and Failure Analysis
PublisherASM International
Pages232-241
Number of pages10
ISBN (Electronic)9781615030866
DOIs
StatePublished - 2003
Event29th International Symposium for Testing and Failure Analysis, ISTFA 2003 - Santa Clara, United States
Duration: Nov 2 2003Nov 6 2003

Publication series

NameConference Proceedings from the International Symposium for Testing and Failure Analysis
Volume2003-November

Conference

Conference29th International Symposium for Testing and Failure Analysis, ISTFA 2003
Country/TerritoryUnited States
CitySanta Clara
Period11/2/0311/6/03

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