@inproceedings{a856a70007c0488698b0725e1c7b03ca,
title = "Application specific coarse-grained FPGA for processing element in real time parallel particle filters",
abstract = "This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 μm CMOS process.",
keywords = "Application software, Computer architecture, Digital signal processing, Field programmable gate arrays, Filtering, Particle filters, Particle tracking, Real time systems, Reconfigurable architectures, Throughput",
author = "M. Sadasivam and Sanjing Hong",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 ; Conference date: 30-06-2003 Through 02-07-2003",
year = "2003",
doi = "10.1109/IWSOC.2003.1213018",
language = "English",
series = "Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "116--119",
editor = "Yehya Ismail and Wael Badawy",
booktitle = "Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003",
}