Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond

Mikhail Dorojevets; Paul Bunyk

doi:10.1109/TASC.2003.813893

Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond

Mikhail Dorojevets
, Paul Bunyk

Electrical Engineering

Northrop Grumman

Research output: Contribution to journal › Conference article › peer-review

22 Scopus citations

Abstract

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm ², 1.75-μm Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm × 10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

Original language	English
Pages (from-to)	446-449
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	13
Issue number	2 I
DOIs	https://doi.org/10.1109/TASC.2003.813893
State	Published - Jun 2003
Event	2002 Applied Superconductivity Conference - Houston, TX, United States Duration: Aug 4 2002 → Aug 9 2002

Keywords

Low-temperature superconductors
Microprocessor design
Petaflops computing
RSFQ logic

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10.1109/TASC.2003.813893

Cite this

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title = "Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond",

abstract = "This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm 2, 1.75-μm Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm × 10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.",

keywords = "Low-temperature superconductors, Microprocessor design, Petaflops computing, RSFQ logic",

author = "Mikhail Dorojevets and Paul Bunyk",

year = "2003",

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N2 - This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm 2, 1.75-μm Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm × 10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

AB - This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm 2, 1.75-μm Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm × 10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

KW - Low-temperature superconductors

KW - Microprocessor design

KW - Petaflops computing

KW - RSFQ logic

UR - https://www.scopus.com/pages/publications/0042476471

U2 - 10.1109/TASC.2003.813893

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JF - IEEE Transactions on Applied Superconductivity

IS - 2 I

Y2 - 4 August 2002 through 9 August 2002

ER -

Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond

Abstract

Keywords

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