Architectures and memory schemes for sampling and resampling in Particle Filters

Particle Filtering is a signal processing method that has recently gained immense popularity in solving several problems in signal processing and communications. This paper presents a part of a larger effort directed towards realizing particle filters (PFs) in hardware. Here we propose two architectures and memory schemes for the resample and the sample steps of the traditional PF known as the Sample Importance Resample Filter (SIRF). Using the proposed architectures, the memory requirement and latency of the SIRF in hardware is significantly reduced as compared to a straightforward implementation starting from the traditional algorithm. The hardware requirements and latency of the two schemes are evaluated and compared. The platform used for the evaluation is the Xilinx Virtex 2 Pro FPGA. The proposed architectures have led to the development of the first hardware prototype for PFs.