@inproceedings{0f99f40164734880ac19290d58fec7f9,
title = "Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer",
abstract = "We present an area-efficient MAP-based turbo equalizer VLSI architecture by proposing a symbol-based soft-input soft-output (SISO) kernel which processes one multi-bit symbol in every clock cycle. The symbol-based SISO hardware can be shared by the equalizer and decoder, thereby reducing silicon area. Further, by introducing block-interleaved computation in the add-compare-select recursions, the critical path delay is reduced, thereby improving throughput. Experimental results with QPSK modulation and K ⊃ 5 encoder demonstrate that the proposed area-efficient architecture achieves area savings of 47\% with 11\% throughput gain in a 0.25 μm CMOS process. It is also shown that the throughput is improved by 79\% via block-interleaved computation with an area savings of 25\%.",
keywords = "Clocks, Computer architecture, Decoding, Delay, Equalizers, Hardware, Kernel, Silicon, Throughput, Very large scale integration",
author = "Lee, \{Seok Jun\} and Shanbhag, \{N. R.\} and Singer, \{A. C.\}",
note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 ; Conference date: 27-08-2003 Through 29-08-2003",
year = "2003",
doi = "10.1109/SIPS.2003.1235649",
language = "English",
series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "87--92",
editor = "Wonyong Sung and Sunwoo, \{Myung Hoon\}",
booktitle = "2003 IEEE Workshop on Signal Processing Systems",
}