Autonomous buffer controller design for concurrent execution in block level pipelined dataflow

Magesh Sadasivam; Sangjin Hong

doi:10.1109/ISVLSI.2004.1339565

Autonomous buffer controller design for concurrent execution in block level pipelined dataflow

Magesh Sadasivam
, Sangjin Hong

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging Trends in VLSI Systems Design
Editors	A. Smailagic, M. Bayoumi
Pages	303-304
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2004.1339565
State	Published - 2004
Event	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States Duration: Feb 19 2004 → Feb 20 2004

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Conference

Conference	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Country/Territory	United States
City	Lafayette, LA
Period	02/19/04 → 02/20/04

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10.1109/ISVLSI.2004.1339565

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Sadasivam, M., & Hong, S. (2004). Autonomous buffer controller design for concurrent execution in block level pipelined dataflow. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 303-304). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339565

Sadasivam, Magesh ; Hong, Sangjin. / Autonomous buffer controller design for concurrent execution in block level pipelined dataflow. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. editor / A. Smailagic ; M. Bayoumi. 2004. pp. 303-304 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

@inproceedings{ce539730ec1549feb718ec728a092acb,

title = "Autonomous buffer controller design for concurrent execution in block level pipelined dataflow",

abstract = "This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.",

author = "Magesh Sadasivam and Sangjin Hong",

year = "2004",

doi = "10.1109/ISVLSI.2004.1339565",

language = "English",

isbn = "0769520979",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design",

pages = "303--304",

editor = "A. Smailagic and M. Bayoumi",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design ; Conference date: 19-02-2004 Through 20-02-2004",

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Sadasivam, M & Hong, S 2004, Autonomous buffer controller design for concurrent execution in block level pipelined dataflow. in A Smailagic & M Bayoumi (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, pp. 303-304, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, Lafayette, LA, United States, 02/19/04. https://doi.org/10.1109/ISVLSI.2004.1339565

Autonomous buffer controller design for concurrent execution in block level pipelined dataflow. / Sadasivam, Magesh; Hong, Sangjin.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. ed. / A. Smailagic; M. Bayoumi. 2004. p. 303-304 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a method of generating configurable controller structure for concurrent processing of memory centric coarse grain data flows. The controller can be incorporated in both proposed block level pipelining and traditional fine grain pipelining. The proposed controller isolates controls for buffer and logic such that system integration is simplified while controllers are locally configured from orthogonal global information.

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Sadasivam M, Hong S. Autonomous buffer controller design for concurrent execution in block level pipelined dataflow. In Smailagic A, Bayoumi M, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. 2004. p. 303-304. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). doi: 10.1109/ISVLSI.2004.1339565

Autonomous buffer controller design for concurrent execution in block level pipelined dataflow

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