Buffer controller-based multiple processing element utilization for dataflow synthesis

This paper presents an effective design methodology which maps a complex system represented as a dataflow graph to a reconfigurable target architecture having multi-core processors and programmable logics. In order to synchronize data transfers between two processing blocks mapped to different processors (alternatively, one block is mapped to a processor and the other is realized as a hardware), we propose a mapping methodology that exploits the buffer-based dataflow, a new representation technique for realizing data-centric applications in reconfigurable platforms. From the buffer-based dataflow and estimated execution times of functional blocks and data transfers, the proposed methodology creates a mapped partition and generates the template code which runs on the processors of the target platform. We also use a processor initiation scheme to prevent wrong operations from happening when actual execution takes longer than estimated. Our proposed mapping methodology and the generated template code are evaluated with the SystemC model and Xilinx ISE.