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Computer generation of streaming sorting networks

  • Swiss Federal Institute of Technology Zurich

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

48 Scopus citations

Abstract

Sorting networks offer great performance but become prohibitively expensive for large data sets. We present a domain-specific language and compiler to automatically generate hardware implementations of sorting networks with reduced area and optimized for latency or throughput. Our results show that the generator produces a wide range of Pareto-optimal solutions that both compete with and outperform prior sorting hardware.

Original languageEnglish
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Pages1245-1253
Number of pages9
DOIs
StatePublished - 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference49th Annual Design Automation Conference, DAC '12
Country/TerritoryUnited States
CitySan Francisco, CA
Period06/3/1206/7/12

Keywords

  • design space exploration
  • hardware sorting
  • HDL generation

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