Decoupling Capacitor Topologies for TSV-Based 3-D ICs with Power Gating

In traditional decoupling capacitor topologies, power gating can significantly degrade the system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance associated with the power-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: 1) relatively low-resistance through silicon vias (TSVs) and 2) ability of TSVs to bypass plane-level power networks when delivering the power supply voltage. In the proposed topologies, decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, achieving up to 50% and 87% reduction in, respectively, rms power supply and power gating (in-rush current) noise at the expense of a moderate increase in physical area and peak power consumption.