TY - GEN
T1 - Design considerations for GaN HEMT multichip halfbridge module for high-frequency power converters
AU - Luo, Fang
AU - Chen, Zheng
AU - Xue, Lingxiao
AU - Mattavelli, Paolo
AU - Boroyevich, Dushan
AU - Hughes, Brian
PY - 2014
Y1 - 2014
N2 - This paper discusses the design of a multichip Gallium-Nitride (GaN) power module for high frequency power conversion. The module is designed with HRL 600 V GalliumNitride (GaN) enhancement mode HEMT device. To exploit the capability of fast switching with low loss from high voltage GaN devices, different layout structures have been analyzed to reduce power loop parasitic inductance and improve switching performance. The approach investigated in this paper is based on a multi-chip module where small current rated dies are placed in parallel to achieve higher current handling capability. Moreover, a transmission-line type gate structure has been proposed to minimize the gate loop inductance and reduce the gate voltage ringing. Finite-Element-Analysis (FEA) and switching circuit simulation show that the multi-layer power loop design can effectively reduce the gate loop inductance and voltage overshoot on the devices. This multi-layer design also improves current sharing of the multi-chip module during switching operation. The transmission-line gate design is also proved in both simulation and experiment to be effective for reducing the gate loop inductance as well as gate loop ringing.
AB - This paper discusses the design of a multichip Gallium-Nitride (GaN) power module for high frequency power conversion. The module is designed with HRL 600 V GalliumNitride (GaN) enhancement mode HEMT device. To exploit the capability of fast switching with low loss from high voltage GaN devices, different layout structures have been analyzed to reduce power loop parasitic inductance and improve switching performance. The approach investigated in this paper is based on a multi-chip module where small current rated dies are placed in parallel to achieve higher current handling capability. Moreover, a transmission-line type gate structure has been proposed to minimize the gate loop inductance and reduce the gate voltage ringing. Finite-Element-Analysis (FEA) and switching circuit simulation show that the multi-layer power loop design can effectively reduce the gate loop inductance and voltage overshoot on the devices. This multi-layer design also improves current sharing of the multi-chip module during switching operation. The transmission-line gate design is also proved in both simulation and experiment to be effective for reducing the gate loop inductance as well as gate loop ringing.
UR - https://www.scopus.com/pages/publications/84900459329
U2 - 10.1109/APEC.2014.6803361
DO - 10.1109/APEC.2014.6803361
M3 - Conference contribution
AN - SCOPUS:84900459329
SN - 9781479923250
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 537
EP - 544
BT - APEC 2014 - 29th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2014
Y2 - 16 March 2014 through 20 March 2014
ER -