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Design methodology for a low-frequency current-starved voltage-controlled oscillator with a frequency divider

  • University of Maryland, College Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

This paper presents a design methodology for a low-frequency oscillator which consists of a current-starved (CS) voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider is used to reduce frequency in an area efficient manner; achieving this by scaling up the sizes of VCO components is impractical for low frequency applications. We derive a model for the effective capacitance of a CSVCO so that design tradeoffs between area, power, and phase noise can be readily explored. The methodology supports optimization over these performance metrics, with adjustable weighting factors that emphasize their relative importance. Design examples in 0.5μm CMOS technology with 3.3 V supply are presented.

Original languageEnglish
Title of host publication2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Pages646-649
Number of pages4
DOIs
StatePublished - 2012
Event2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012 - Boise, ID, United States
Duration: Aug 5 2012Aug 8 2012

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference2012 IEEE 55th International Midwest Symposium on Circuits and Systems, MWSCAS 2012
Country/TerritoryUnited States
CityBoise, ID
Period08/5/1208/8/12

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