TY - GEN
T1 - Dual quadtree representation for VLSI designs
AU - Nandy, S. K.
AU - Ramakrishnan, I. V.
N1 - Publisher Copyright:
© 1986 IEEE.
PY - 1986/7/2
Y1 - 1986/7/2
N2 - The Quad-CIF tree has been proposed as a data structure for hierarchical design of VLSI. Frequently encountered operations in VLSI design require a lot of serach effort on a Quad-CIF tree. Additionally, since the empty spaces are not explicitly stored in the tree, layout compaction is difficult to achieve. To support such operations efficiently, we propose a dual quadtree structure for VLSI design. At the first level we represent a cell in the layout as a "painted quadtree". The painted quadtree stores the entire region spanned by all the rectangles in the cell. Once the cell is designed it is stored in the form of boundary codes. At the second level of the dual structure, these boundary codes are stored in a Quad-CIF tree. Therefore, the dual structure affords us the convenience of using the painted quadtree for interactive design and the excellent features of the Quad-CIF tree for hierarchical design and compact storage representation.
AB - The Quad-CIF tree has been proposed as a data structure for hierarchical design of VLSI. Frequently encountered operations in VLSI design require a lot of serach effort on a Quad-CIF tree. Additionally, since the empty spaces are not explicitly stored in the tree, layout compaction is difficult to achieve. To support such operations efficiently, we propose a dual quadtree structure for VLSI design. At the first level we represent a cell in the layout as a "painted quadtree". The painted quadtree stores the entire region spanned by all the rectangles in the cell. Once the cell is designed it is stored in the form of boundary codes. At the second level of the dual structure, these boundary codes are stored in a Quad-CIF tree. Therefore, the dual structure affords us the convenience of using the painted quadtree for interactive design and the excellent features of the Quad-CIF tree for hierarchical design and compact storage representation.
UR - https://www.scopus.com/pages/publications/84956443065
U2 - 10.1109/DAC.1986.1586160
DO - 10.1109/DAC.1986.1586160
M3 - Conference contribution
AN - SCOPUS:84956443065
SN - 0818607025
T3 - Proceedings - Design Automation Conference
SP - 663
EP - 666
BT - Proceedings of the 23rd ACM/IEEE Design Automation Conference, DAC 1986
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd ACM/IEEE Design Automation Conference, DAC 1986
Y2 - 29 June 1986 through 2 July 1986
ER -