Dynamic coarse grain dataflowreconfiguration technique for real-time systems design

Xiaoyao Liang; Akshay Athalye; Sangjin Hong

doi:10.1109/ISCAS.2005.1465386

Dynamic coarse grain dataflowreconfiguration technique for real-time systems design

Xiaoyao Liang
, Akshay Athalye
, Sangjin Hong

Electrical Engineering

Stony Brook University

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnect. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. In this paper, we discuss dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

Original language	English
Article number	1465386
Pages (from-to)	3511-3514
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465386
State	Published - 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005

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10.1109/ISCAS.2005.1465386

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title = "Dynamic coarse grain dataflowreconfiguration technique for real-time systems design",

abstract = "This paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnect. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. In this paper, we discuss dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.",

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AU - Liang, Xiaoyao

AU - Athalye, Akshay

AU - Hong, Sangjin

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N2 - This paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnect. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. In this paper, we discuss dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

AB - This paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnect. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. In this paper, we discuss dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

UR - https://www.scopus.com/pages/publications/47749133718

U2 - 10.1109/ISCAS.2005.1465386

DO - 10.1109/ISCAS.2005.1465386

M3 - Conference article

AN - SCOPUS:47749133718

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SP - 3511

EP - 3514

JO - Proceedings - IEEE International Symposium on Circuits and Systems

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M1 - 1465386

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Dynamic coarse grain dataflowreconfiguration technique for real-time systems design

Abstract

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