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Effect of TSV fabrication technology on power distribution in 3D ICs

  • NVIDIA

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

The design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to develop equivalent electrical models for both via-first and via-last based power distribution networks. Based on these models, a valid design space has been developed where power supply noise is satisfied and physical area overhead is minimized. Under constant power supply noise, a via-last based power network occupies 7.5% less area. However, in addition to causing routing blockages, a via-last based power network exhibits high sensitivity to design parameters due to a high quality factor. Alternatively, a via-first based power network requires a large number of TSVs, but exhibits relatively more predictable behavior due to a lower quality factor (higher damping).

Original languageEnglish
Title of host publicationGLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
Pages287-292
Number of pages6
DOIs
StatePublished - 2013
Event23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013 - Paris, France
Duration: May 2 2013May 3 2013

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
Country/TerritoryFrance
CityParis
Period05/2/1305/3/13

Keywords

  • 3d ic
  • power noise
  • tsv

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