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Efficient characterization of TSV-to-transistor noise coupling in 3D ICs

  • Stony Brook University
  • Columbia University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

A methodology is proposed to characterize TSV induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using a 3D transmission line matrix (3D-TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type and placement of substrate contacts.

Original languageEnglish
Title of host publicationGLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
Pages71-76
Number of pages6
DOIs
StatePublished - 2013
Event23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013 - Paris, France
Duration: May 2 2013May 3 2013

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
Country/TerritoryFrance
CityParis
Period05/2/1305/3/13

Keywords

  • 3d ic
  • compact model
  • noise
  • tsv

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