TY - GEN
T1 - Electrical-Thermal-Mechanical Considerations for the Design of a Compact Two-Level Current Source Inverter using GaN Devices
AU - Mustafeez-Ul-Hassan,
AU - Wu, Yuxuan
AU - Emon, Asif Imran
AU - Yuan, Zhao
AU - Luo, Fang
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents an application of GaN devices for the development of a low temperature current source inverter (CSI) meant for higher efficiency and power density applications targeting future electric aircrafts. A detailed investigation about influence of layout parasitics onto device over voltages and output voltage waveform is carried out. The paper optimizes the commutation loop by having a 'Y' shaped layout for CSI with the lowest ever re-ported inductance of 3.51 nH. The paper also discusses the CSI inverter design from thermal and mechanical aspects and their impact on electrical performance. The design concept is validated with three phase experiments using GaN devices, by developing two different configurations of CSI, where design of commutation loop inductance has also been verified by double pulse test (DPT) results. The paper presents detailed analysis and trade-offs between commutation loop optimization, and its impact on gate driver placement, and mechanical assembly.
AB - This paper presents an application of GaN devices for the development of a low temperature current source inverter (CSI) meant for higher efficiency and power density applications targeting future electric aircrafts. A detailed investigation about influence of layout parasitics onto device over voltages and output voltage waveform is carried out. The paper optimizes the commutation loop by having a 'Y' shaped layout for CSI with the lowest ever re-ported inductance of 3.51 nH. The paper also discusses the CSI inverter design from thermal and mechanical aspects and their impact on electrical performance. The design concept is validated with three phase experiments using GaN devices, by developing two different configurations of CSI, where design of commutation loop inductance has also been verified by double pulse test (DPT) results. The paper presents detailed analysis and trade-offs between commutation loop optimization, and its impact on gate driver placement, and mechanical assembly.
UR - https://www.scopus.com/pages/publications/85162226242
U2 - 10.1109/APEC43580.2023.10131491
DO - 10.1109/APEC43580.2023.10131491
M3 - Conference contribution
AN - SCOPUS:85162226242
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 854
EP - 861
BT - APEC 2023 - 38th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 38th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2023
Y2 - 19 March 2023 through 23 March 2023
ER -