TY - GEN
T1 - EQUAL
T2 - 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
AU - Dhananjay, Krithika
AU - Salman, Emre
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/7
Y1 - 2021/7
N2 - Adiabatic circuits have the potential to achieve ultra-low power consumption while also exhibiting inherent resistance against power side-channel attacks. A novel adiabatic logic family is proposed in this work with application to lightweight devices where both energy efficiency and hardware security are of primary concern. The side-channel security characteristics of the proposed adiabatic logic are evaluated by quantifying normalized energy deviation (NED) and the normalized standard deviation (NSD). These metrics are compared with the existing secure adiabatic logic families. The simulations are performed at an RFID frequency of 13.56 MHz using a 65 nm technology node. The average energy per transition consumed by the NAND/AND and NOR/OR gates in the proposed logic family is up to 34.5% lower at the expense of 3% increase in the NED and 1.5% increase in the NSD. The proposed approach also reduces the number of transistors by 40%. Furthermore, the proposed adiabatic logic family does not require any external four-phase input signals to achieve input-independent power consumption, thereby significantly reducing the overall overhead.
AB - Adiabatic circuits have the potential to achieve ultra-low power consumption while also exhibiting inherent resistance against power side-channel attacks. A novel adiabatic logic family is proposed in this work with application to lightweight devices where both energy efficiency and hardware security are of primary concern. The side-channel security characteristics of the proposed adiabatic logic are evaluated by quantifying normalized energy deviation (NED) and the normalized standard deviation (NSD). These metrics are compared with the existing secure adiabatic logic families. The simulations are performed at an RFID frequency of 13.56 MHz using a 65 nm technology node. The average energy per transition consumed by the NAND/AND and NOR/OR gates in the proposed logic family is up to 34.5% lower at the expense of 3% increase in the NED and 1.5% increase in the NSD. The proposed approach also reduces the number of transistors by 40%. Furthermore, the proposed adiabatic logic family does not require any external four-phase input signals to achieve input-independent power consumption, thereby significantly reducing the overall overhead.
UR - https://www.scopus.com/pages/publications/85114961710
U2 - 10.1109/ISVLSI51109.2021.00067
DO - 10.1109/ISVLSI51109.2021.00067
M3 - Conference contribution
AN - SCOPUS:85114961710
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 332
EP - 337
BT - Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
PB - IEEE Computer Society
Y2 - 7 July 2021 through 9 July 2021
ER -