Error Probability Models to Facilitate Approximate Computing in TFET based Circuits

Mallika Rathore; Emre Salman

doi:10.1109/ISCAS.2018.8351214

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits

Mallika Rathore
, Emre Salman

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

A probabilistic approach is developed to evaluate the impact of power supply voltage fluctuations on the output error probability of tunnel field-effect transistor (TFET) based integrated circuits (ICs) operating at low supply voltages. The proposed model is used to better understand the error probability of synchronous digital circuits designed with 22 nm III-V heterojunction TFET technology. A comparative analysis with high performance 20 nm FinFET and 22 nm CMOS based circuits is also provided to illustrate the related tradeoffs among supply voltage, frequency, and error probability for these three technologies. This investigation is important for energy-efficient TFET based circuits where noise sensitivity is higher due to ultra low operating voltages.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538648810
DOIs	https://doi.org/10.1109/ISCAS.2018.8351214
State	Published - Apr 26 2018
Event	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy Duration: May 27 2018 → May 30 2018

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2018-May
ISSN (Print)	0271-4310

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Country/Territory	Italy
City	Florence
Period	05/27/18 → 05/30/18

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10.1109/ISCAS.2018.8351214

Cite this

Rathore, M., & Salman, E. (2018). Error Probability Models to Facilitate Approximate Computing in TFET based Circuits. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351214 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2018.8351214

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title = "Error Probability Models to Facilitate Approximate Computing in TFET based Circuits",

abstract = "A probabilistic approach is developed to evaluate the impact of power supply voltage fluctuations on the output error probability of tunnel field-effect transistor (TFET) based integrated circuits (ICs) operating at low supply voltages. The proposed model is used to better understand the error probability of synchronous digital circuits designed with 22 nm III-V heterojunction TFET technology. A comparative analysis with high performance 20 nm FinFET and 22 nm CMOS based circuits is also provided to illustrate the related tradeoffs among supply voltage, frequency, and error probability for these three technologies. This investigation is important for energy-efficient TFET based circuits where noise sensitivity is higher due to ultra low operating voltages.",

author = "Mallika Rathore and Emre Salman",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

year = "2018",

month = apr,

day = "26",

doi = "10.1109/ISCAS.2018.8351214",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",

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Rathore, M & Salman, E 2018, Error Probability Models to Facilitate Approximate Computing in TFET based Circuits. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351214, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2018-May, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 05/27/18. https://doi.org/10.1109/ISCAS.2018.8351214

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits. / Rathore, Mallika; Salman, Emre.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8351214 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2018-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Error Probability Models to Facilitate Approximate Computing in TFET based Circuits

AU - Rathore, Mallika

AU - Salman, Emre

PY - 2018/4/26

Y1 - 2018/4/26

N2 - A probabilistic approach is developed to evaluate the impact of power supply voltage fluctuations on the output error probability of tunnel field-effect transistor (TFET) based integrated circuits (ICs) operating at low supply voltages. The proposed model is used to better understand the error probability of synchronous digital circuits designed with 22 nm III-V heterojunction TFET technology. A comparative analysis with high performance 20 nm FinFET and 22 nm CMOS based circuits is also provided to illustrate the related tradeoffs among supply voltage, frequency, and error probability for these three technologies. This investigation is important for energy-efficient TFET based circuits where noise sensitivity is higher due to ultra low operating voltages.

AB - A probabilistic approach is developed to evaluate the impact of power supply voltage fluctuations on the output error probability of tunnel field-effect transistor (TFET) based integrated circuits (ICs) operating at low supply voltages. The proposed model is used to better understand the error probability of synchronous digital circuits designed with 22 nm III-V heterojunction TFET technology. A comparative analysis with high performance 20 nm FinFET and 22 nm CMOS based circuits is also provided to illustrate the related tradeoffs among supply voltage, frequency, and error probability for these three technologies. This investigation is important for energy-efficient TFET based circuits where noise sensitivity is higher due to ultra low operating voltages.

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U2 - 10.1109/ISCAS.2018.8351214

DO - 10.1109/ISCAS.2018.8351214

M3 - Conference contribution

AN - SCOPUS:85057094229

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits

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