Evaluating power-performance trade-offs of VLSI transceiver architecture for low-energy communication system design

A VLSI transceiver power-performance evaluation methodology for low-energy communication system design is presented. Both functional and architectural aspects of the system are modeled. The methodology simultaneously considers system performance and architectural models for the evaluation. Two models are closely linked by a set of common parameters, which affects both the performance and the hardware complexity. In the methodology, various major blocks, including channel coding algorithms, demodulation schemes, and synchronization techniques can be rapidly reconfigured and parameterized. The minimum power dissipation solution is searched by the unidirectional steepest descent method to explore the design solution space. With the presented methodology, rapid evaluation of algorithms and the power consumption are feasible and the design tradeoffs can be made.