Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 1.2kV 4H-SiC Power MOSFETs

Several 1.2kV 4H-SiC devices of various cell architectures have been successfully fabricated by employing different P+ implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities across the different device designs. It was found that by utilizing devices designed with an orthogonal P+ source layout as opposed to the traditional P+ stripe pattern, the long-term reliability under sustained 3rd Quadrant current stress conduction can be greatly improved even in devices with medium BPD densities. In addition, the use of the unipolar current of the JBSFET can further enhance long-term reliability under sustained 3^rd Quadrant current stress by mitigating stacking fault expansion, even in devices with a high BPD density.