TY - GEN
T1 - Extended counting ADC for 32-channel neural recording headstage for small animals
AU - Yun, Xiao
AU - Stanaćević, Milutin
PY - 2008
Y1 - 2008
N2 - Extended counting analog-to-digital converter (ECADC) combines the accuracy of delta-sigma modulation and the speed of algorithmic conversion. This conversion architecture is shown to be useful in biomedical applications, where both resolution and speed are demanded. This work presents a design of ECADC for 32 neural recording channels. Several power optimizing methods are described. The designed converter achieves a resolution of 13 bits and a sampling frequency of 512 kHz. With 3.3V supply, the total power consumption is estimated to be 7 mW. The whole system including 32 neural recording channels is fitted in an area of 3mm x 3mm in 0.5μm CMOS process.
AB - Extended counting analog-to-digital converter (ECADC) combines the accuracy of delta-sigma modulation and the speed of algorithmic conversion. This conversion architecture is shown to be useful in biomedical applications, where both resolution and speed are demanded. This work presents a design of ECADC for 32 neural recording channels. Several power optimizing methods are described. The designed converter achieves a resolution of 13 bits and a sampling frequency of 512 kHz. With 3.3V supply, the total power consumption is estimated to be 7 mW. The whole system including 32 neural recording channels is fitted in an area of 3mm x 3mm in 0.5μm CMOS process.
UR - https://www.scopus.com/pages/publications/51749083230
U2 - 10.1109/ISCAS.2008.4541966
DO - 10.1109/ISCAS.2008.4541966
M3 - Conference contribution
AN - SCOPUS:51749083230
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2510
EP - 2513
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -