TY - GEN
T1 - Fast Concurrent Primitives Despite Contention
AU - Bender, Michael A.
AU - Blelloch, Guy E.
AU - Farach-Colton, Martin
AU - Hu, Yang
AU - Johnson, Rob
AU - Oshman, Rotem
AU - Zhou, Renfei
N1 - Publisher Copyright:
© 2026 Copyright held by the owner/author(s).
PY - 2026/7/8
Y1 - 2026/7/8
N2 - We study the problem of constructing concurrent objects in a setting where P processes run in parallel and interact through a shared memory that is subject to write contention. Our goal is to transform hardware primitives that are subject to write contention into ones that handle contention gracefully.We give contention-resolution algorithms for several basic primitives, and analyze them under a relaxed, roughly-synchronous stochastic scheduler, where processes run at roughly the same rate up to a constant factor with high probability. Specifically, we construct read/write registers and CAS registers that have latency O(log P) w.h.p. under our scheduler model, using O(1) hardware read/write registers and, in the case of our CAS construction, one hardware CAS register. Our algorithms guarantee performance even when their operations are invoked by an adaptive adversary that is able to see the entire history of operations so far, including their timing and return values. This allows them to be used as building blocks inside larger programs; using this compositionality property, we obtain several other constructions (LL/SC, fetch-and-increment, bounded max registers, and counters).To complement our constructions, we give a trade-off showing that even under a perfectly synchronous schedule and even if each process only executes one operation, any algorithm that implements any of the primitives that we consider, uses space M, and has latency at most L with high probability must have expected latency at least ω(logMLP).
AB - We study the problem of constructing concurrent objects in a setting where P processes run in parallel and interact through a shared memory that is subject to write contention. Our goal is to transform hardware primitives that are subject to write contention into ones that handle contention gracefully.We give contention-resolution algorithms for several basic primitives, and analyze them under a relaxed, roughly-synchronous stochastic scheduler, where processes run at roughly the same rate up to a constant factor with high probability. Specifically, we construct read/write registers and CAS registers that have latency O(log P) w.h.p. under our scheduler model, using O(1) hardware read/write registers and, in the case of our CAS construction, one hardware CAS register. Our algorithms guarantee performance even when their operations are invoked by an adaptive adversary that is able to see the entire history of operations so far, including their timing and return values. This allows them to be used as building blocks inside larger programs; using this compositionality property, we obtain several other constructions (LL/SC, fetch-and-increment, bounded max registers, and counters).To complement our constructions, we give a trade-off showing that even under a perfectly synchronous schedule and even if each process only executes one operation, any algorithm that implements any of the primitives that we consider, uses space M, and has latency at most L with high probability must have expected latency at least ω(logMLP).
KW - concurrent data structures
KW - contention
KW - randomized algorithms
KW - shared memory
UR - https://www.scopus.com/pages/publications/105044840853
U2 - 10.1145/3816782.3819207
DO - 10.1145/3816782.3819207
M3 - Conference contribution
AN - SCOPUS:105044840853
T3 - Annual ACM Symposium on Parallelism in Algorithms and Architectures
SP - 196
EP - 233
BT - Proceedings of the 38th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 26
PB - Association for Computing Machinery
T2 - 38th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2026
Y2 - 6 July 2026 through 10 July 2026
ER -