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FAULT-TOLERANT MULTIPIPELINE ARCHITECTURE.

  • Stony Brook University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The authors address the problem of recovering identical pipelines in the presence of faulty stages. Such pipelines are typically used in vector supercomputers. The authors alternate the pipeline stages with testing and reconfiguring circuitry, which is assumed to be fault free. The pipelines are reconfigured by programming the switches in a distributed manner. The switch programming algorithm is optimized to recover the maximum number of pipelines under any fault pattern. A proof of its optimality is also presented. Probabilistic bounds on the delay (the number of bypased faulty stages) and yield (the number of nonfaulty pipelines recovered) are derived. The authors show that the maximum signal delay in any of the pipelines is THETA (logm), where m is the initial number of pipelines. Furthermore, a constant fraction of these pipelines can be recovered with this scheme, as opposed to an exponentially decreasing number when no reconfiguration is used.

Original languageEnglish
Title of host publicationDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
PublisherIEEE
Pages350-355
Number of pages6
ISBN (Print)0818607033
StatePublished - 1986

Publication series

NameDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
ISSN (Print)0731-3071

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