FAULT-TOLERANT VLSI MATRIX MULTIPLIER.

P. J. Varman; I. V. Ramakrishnan

FAULT-TOLERANT VLSI MATRIX MULTIPLIER.

P. J. Varman
, I. V. Ramakrishnan

Computer Science

Rice University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The authors have previously presented a computing structure that has all the attractive implementation features of a linear array but can multiply matrices with a better time performance. The interrelationship among the number of processors, the storage within a processor, the internal bandwidth and the time complexity of matrix multiplication on such a model is examined. Lower bounds are established on the time complexity and the number of processors required as a function of the storage within a processor and the internal bandwidth. A generalized algorithm which matches these bounds for arbitrary storage within a processor and arbitrary bandwidth is presented.

Original language	English
Title of host publication	Proceedings of the International Conference on Parallel Processing
Editors	Kai Hwang, Steven M. Jacobs, Earl E. Swartzlander
Publisher	IEEE
Pages	351-357
Number of pages	7
ISBN (Print)	0818607246
State	Published - 1986

Publication series

Name	Proceedings of the International Conference on Parallel Processing
ISSN (Print)	0190-3918

Cite this

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title = "FAULT-TOLERANT VLSI MATRIX MULTIPLIER.",

abstract = "The authors have previously presented a computing structure that has all the attractive implementation features of a linear array but can multiply matrices with a better time performance. The interrelationship among the number of processors, the storage within a processor, the internal bandwidth and the time complexity of matrix multiplication on such a model is examined. Lower bounds are established on the time complexity and the number of processors required as a function of the storage within a processor and the internal bandwidth. A generalized algorithm which matches these bounds for arbitrary storage within a processor and arbitrary bandwidth is presented.",

author = "Varman, \{P. J.\} and Ramakrishnan, \{I. V.\}",

year = "1986",

language = "English",

isbn = "0818607246",

series = "Proceedings of the International Conference on Parallel Processing",

publisher = "IEEE",

pages = "351--357",

editor = "Kai Hwang and Jacobs, \{Steven M.\} and Swartzlander, \{Earl E.\}",

booktitle = "Proceedings of the International Conference on Parallel Processing",

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FAULT-TOLERANT VLSI MATRIX MULTIPLIER. / Varman, P. J.; Ramakrishnan, I. V.
Proceedings of the International Conference on Parallel Processing. ed. / Kai Hwang; Steven M. Jacobs; Earl E. Swartzlander. IEEE, 1986. p. 351-357 (Proceedings of the International Conference on Parallel Processing).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FAULT-TOLERANT VLSI MATRIX MULTIPLIER.

AU - Varman, P. J.

AU - Ramakrishnan, I. V.

PY - 1986

Y1 - 1986

N2 - The authors have previously presented a computing structure that has all the attractive implementation features of a linear array but can multiply matrices with a better time performance. The interrelationship among the number of processors, the storage within a processor, the internal bandwidth and the time complexity of matrix multiplication on such a model is examined. Lower bounds are established on the time complexity and the number of processors required as a function of the storage within a processor and the internal bandwidth. A generalized algorithm which matches these bounds for arbitrary storage within a processor and arbitrary bandwidth is presented.

AB - The authors have previously presented a computing structure that has all the attractive implementation features of a linear array but can multiply matrices with a better time performance. The interrelationship among the number of processors, the storage within a processor, the internal bandwidth and the time complexity of matrix multiplication on such a model is examined. Lower bounds are established on the time complexity and the number of processors required as a function of the storage within a processor and the internal bandwidth. A generalized algorithm which matches these bounds for arbitrary storage within a processor and arbitrary bandwidth is presented.

UR - https://www.scopus.com/pages/publications/0022913723

M3 - Conference contribution

AN - SCOPUS:0022913723

SN - 0818607246

T3 - Proceedings of the International Conference on Parallel Processing

SP - 351

EP - 357

BT - Proceedings of the International Conference on Parallel Processing

A2 - Hwang, Kai

A2 - Jacobs, Steven M.

A2 - Swartzlander, Earl E.

PB - IEEE

ER -

FAULT-TOLERANT VLSI MATRIX MULTIPLIER.

Abstract

Publication series

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