Flux-1 RSFQ microprocessor: Physical design and test results

Paul Bunyk; Mike Leung; John Spargo; Mikhail Dorojevets

doi:10.1109/TASC.2003.813890

Flux-1 RSFQ microprocessor: Physical design and test results

Paul Bunyk
, Mike Leung
, John Spargo
, Mikhail Dorojevets

Electrical Engineering

Northrop Grumman

Research output: Contribution to journal › Conference article › peer-review

53 Scopus citations

Abstract

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification. A companion paper describes Flux-1 architecture.

Original language	English
Pages (from-to)	433-436
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	13
Issue number	2 I
DOIs	https://doi.org/10.1109/TASC.2003.813890
State	Published - Jun 2003
Event	2002 Applied Superconductivity Conference - Houston, TX, United States Duration: Aug 4 2002 → Aug 9 2002

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abstract = "The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification. A companion paper describes Flux-1 architecture.",

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AB - The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification. A companion paper describes Flux-1 architecture.

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Y2 - 4 August 2002 through 9 August 2002

ER -

Flux-1 RSFQ microprocessor: Physical design and test results

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