TY - GEN
T1 - Frontend Electronic System for Triboelectric Harvester in a Smart Knee Implant
AU - Jain, Manav
AU - Ibrahim, Alwathiqbellah
AU - Salman, Emre
AU - Stanacevic, Milutin
AU - Willing, Ryan
AU - Towfighian, Shahrzad
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/8
Y1 - 2019/8
N2 - Total knee replacement (TKR) is an increasingly common surgery, particularly among active young and elderly people who suffer from knee pain. Continuous monitoring of the load on the knee after the surgery is highly desirable for designing an efficient and more functional smart knee implant. This study involves designing a triboelectric harvester to produce a signal, which is used by the proposed frontend electronic system to monitor the load. At a knee cyclic load of 2.3 kN, the harvester produces 6 μW power and 18 V RMS signal at a frequency of 1 Hz. This paper proposes a novel self-powered frontend electronic system to process this harvested signal and monitor the load on the knee. First, an electrical model is generated for the fabricated harvester. In the next step, the output signal is processed using a filter, rectifier and regulator, and finally converted into digital bits using an analog-to-digital converter. The power consumption of the proposed design is 5.25 μW.
AB - Total knee replacement (TKR) is an increasingly common surgery, particularly among active young and elderly people who suffer from knee pain. Continuous monitoring of the load on the knee after the surgery is highly desirable for designing an efficient and more functional smart knee implant. This study involves designing a triboelectric harvester to produce a signal, which is used by the proposed frontend electronic system to monitor the load. At a knee cyclic load of 2.3 kN, the harvester produces 6 μW power and 18 V RMS signal at a frequency of 1 Hz. This paper proposes a novel self-powered frontend electronic system to process this harvested signal and monitor the load on the knee. First, an electrical model is generated for the fabricated harvester. In the next step, the output signal is processed using a filter, rectifier and regulator, and finally converted into digital bits using an analog-to-digital converter. The power consumption of the proposed design is 5.25 μW.
UR - https://www.scopus.com/pages/publications/85075002975
U2 - 10.1109/MWSCAS.2019.8884972
DO - 10.1109/MWSCAS.2019.8884972
M3 - Conference contribution
AN - SCOPUS:85075002975
T3 - Midwest Symposium on Circuits and Systems
SP - 386
EP - 389
BT - 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019
Y2 - 4 August 2019 through 7 August 2019
ER -