Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs

Circuit camouflaging is a layout-level technique to thwart image analysis-based reverse engineering attacks. An efficient dummy contact-based camouflaging method for monolithic 3-D integrated circuits (ICs) is proposed. 3-D ICs achieve ultra-high density device integration enabled by fine-grained monolithic inter-tier vias. Standard cell libraries are developed to evaluate the effects of circuit camouflaging on large-scale 2-D and monolithic 3-D ICs. These libraries are used to design a camouflaged SIMON (lightweight block cipher) and several academic benchmarks. Simulation results demonstrate that the monolithic 3-D technology is highly effective to facilitate the utilization of the camouflaging technique against reverse engineering attacks. At the expense of a slight degradation in timing characteristics, monolithic 3-D technology eliminates not only the area but also the power overhead related to camouflaging.