Skip to main navigation Skip to search Skip to main content

Hardware implementation of the discrete fourier transform with non-power-of-two problem size

  • Carnegie Mellon University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

15 Scopus citations

Abstract

In this paper, we examine several algorithms suitable for the hardware implementation of the discrete Fourier transform (DFT) with non-power-of two problem size. We incorporate these algorithms into Spiral, a tool capable of automatically generating corresponding hardware implementations. We discuss how each algorithm can be used to generate different types of hardware structures, and we demonstrate that our tool is able to produce hardware implementations of non-powerof-two sized DFTs over a wide range of cost/performance tradeoff points.

Original languageEnglish
Title of host publication2010 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2010 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1546-1549
Number of pages4
ISBN (Print)9781424442966
DOIs
StatePublished - 2010
Event2010 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2010 - Dallas, TX, United States
Duration: Mar 14 2010Mar 19 2010

Publication series

NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ISSN (Print)1520-6149

Conference

Conference2010 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2010
Country/TerritoryUnited States
CityDallas, TX
Period03/14/1003/19/10

Keywords

  • Algorithms
  • Discrete fourier transform
  • Field-programmable gate array
  • FPGA
  • High-level synthesis

Fingerprint

Dive into the research topics of 'Hardware implementation of the discrete fourier transform with non-power-of-two problem size'. Together they form a unique fingerprint.

Cite this