Hardware-software co-design of resource constrained systems on a chip

This paper presents a hardware-software co-design methodology for resource constrained SoC fabricated in a deep submicron process. The novelty of the methodology consists in contemplating critical hardware and layout aspects during system level design for latency optimization. The effect of interconnect parasitic and delays is considered for characterizing bus speed and data communication times. The methodology permits coarse and medium grained resource sharing across tasks for execution speedup through superior usage of hardware. The paper offers experiments for the proposed co-design methodology, including a JPEG SoC.