Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

Alex Doboli; Nagu Dhanwada; Ranga Vemuri

doi:10.1109/ISCAS.2000.856026

Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

Alex Doboli
, Nagu Dhanwada
, Ranga Vemuri

Electrical Engineering

University of Cincinnati

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.

Original language	English
Pages (from-to)	III-181-III-184
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/ISCAS.2000.856026
State	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: May 28 2000 → May 31 2000

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10.1109/ISCAS.2000.856026

Cite this

@article{4deb2de7f7aa4840bcd1044288997846,

title = "Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems",

abstract = "This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.",

author = "Alex Doboli and Nagu Dhanwada and Ranga Vemuri",

year = "2000",

doi = "10.1109/ISCAS.2000.856026",

language = "English",

volume = "3",

pages = "III--181--III--184",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

}

TY - JOUR

T1 - Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

AU - Doboli, Alex

AU - Dhanwada, Nagu

AU - Vemuri, Ranga

PY - 2000

Y1 - 2000

N2 - This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.

AB - This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do.

UR - https://www.scopus.com/pages/publications/0033717845

U2 - 10.1109/ISCAS.2000.856026

DO - 10.1109/ISCAS.2000.856026

M3 - Conference article

AN - SCOPUS:0033717845

SN - 0271-4310

VL - 3

SP - III-181-III-184

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000

Y2 - 28 May 2000 through 31 May 2000

ER -

Heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

Abstract

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