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Hierarchical performance optimization for synthesis of linear analog systems

  • University of Cincinnati

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a hierarchical performance optimization method for high level synthesis of analog systems. The goal is to minimize silicon area while meeting design constraints i.e. AC behavior, op amp gains, slew-rate, power etc. The technique is organized as two successive steps: (1) gain distribution for assigning gains to circuits; and (2) actual performance optimization for finding design parameters that minimize area, realize the assigned circuit gains and meet imposed design constraints. Our experiments show that the proposed method successfully synthesizes analog designs such as filters or communication systems in a reasonable length of time.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
PublisherIEEE Computer Society
Pages431-434
Number of pages4
ISBN (Print)0780366859, 9780780366855
DOIs
StatePublished - 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: May 6 2001May 9 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume5

Conference

Conference2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/TerritoryAustralia
CitySydney, NSW
Period05/6/0105/9/01

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