TY - GEN
T1 - High-speed multicast scheduling for all-optical packet switches
AU - Guo, Zhiyang
AU - Yang, Yuanyuan
PY - 2013
Y1 - 2013
N2 - In this paper, we study multicast scheduling in all-optical packet switches. We first propose a novel optical buffer called multicast-enabled Fiber-Delay-Lines (M-FDLs), which can provide flexible delay for copies of multicast packets using only a small number of FDL segments. We then present a Delay-Guaranteed Multicast Scheduling (DGMS) algorithm that considers the schedule of each arriving packet for multiple time slots. We show that DGMS has several desirable features, such as guaranteed delay upper bound and adaptivity to transmission requirements. To relax the time constraint of DGMS, we further propose a parallel and pipeline architecture for DGMS that distributes the scheduling task to multiple pipelined processing stages, with N processors in each stage, where N is the switch size. Finally, by using a simple combination logic circuit, we show that each processor can finish the scheduling for one time slot in O(1) time. The performance of DGMS is tested extensively against statistical traffic models and real Internet traffic, and the results show that the proposed DGMS algorithm can achieve ultra-low average packet delay with minimum packet drop ratio.
AB - In this paper, we study multicast scheduling in all-optical packet switches. We first propose a novel optical buffer called multicast-enabled Fiber-Delay-Lines (M-FDLs), which can provide flexible delay for copies of multicast packets using only a small number of FDL segments. We then present a Delay-Guaranteed Multicast Scheduling (DGMS) algorithm that considers the schedule of each arriving packet for multiple time slots. We show that DGMS has several desirable features, such as guaranteed delay upper bound and adaptivity to transmission requirements. To relax the time constraint of DGMS, we further propose a parallel and pipeline architecture for DGMS that distributes the scheduling task to multiple pipelined processing stages, with N processors in each stage, where N is the switch size. Finally, by using a simple combination logic circuit, we show that each processor can finish the scheduling for one time slot in O(1) time. The performance of DGMS is tested extensively against statistical traffic models and real Internet traffic, and the results show that the proposed DGMS algorithm can achieve ultra-low average packet delay with minimum packet drop ratio.
KW - Delay guaranteed
KW - Hardware implementation
KW - Multicast scheduling
KW - Optical buffer
KW - Optical packet switching
KW - Parallel
KW - Pipeline
UR - https://www.scopus.com/pages/publications/84893239697
U2 - 10.1109/NAS.2013.26
DO - 10.1109/NAS.2013.26
M3 - Conference contribution
AN - SCOPUS:84893239697
SN - 9780769550343
T3 - Proceedings - 2013 IEEE 8th International Conference on Networking, Architecture and Storage, NAS 2013
SP - 156
EP - 165
BT - Proceedings - 2013 IEEE 8th International Conference on Networking, Architecture and Storage, NAS 2013
T2 - 2013 IEEE 8th International Conference on Networking, Architecture and Storage, NAS 2013
Y2 - 17 July 2013 through 19 July 2013
ER -