TY - GEN
T1 - Impact of low-doped substrate areas on the reliability of circuits subject to EFT events
AU - Secareanu, Radu
AU - Hartin, Olin
AU - Feddeler, Jim
AU - Moseley, Richard
AU - Shepherd, John
AU - Vrignon, Bertrand
AU - Yang, Jian
AU - Li, Qiang
AU - Zhao, Hongwei
AU - Li, Waley
AU - Wei, Linpeng
AU - Salman, Emre
AU - Wang, Richard
AU - Blomberg, Dan
AU - Parris, Patrice
PY - 2010
Y1 - 2010
N2 - External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClev el either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.
AB - External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClev el either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.
UR - https://www.scopus.com/pages/publications/79851499059
U2 - 10.1109/SOCDC.2010.5682984
DO - 10.1109/SOCDC.2010.5682984
M3 - Conference contribution
AN - SCOPUS:79851499059
SN - 9781424486335
T3 - 2010 International SoC Design Conference, ISOCC 2010
SP - 21
EP - 24
BT - 2010 International SoC Design Conference, ISOCC 2010
T2 - 2010 International SoC Design Conference, ISOCC 2010
Y2 - 22 November 2010 through 23 November 2010
ER -