Implement and parameter design of DPLL for invertors based on cycle control

This paper focused on the modelling and parameter design of a period-controlled fully digital phase-locked loop. Although the zero crossing detection DPLL can be implemented easily and conveniently, it lies in the inability when the synchronization signal has multi-zero-crossing resulting from harmonics and spikes. To resolve this problem, a new phase detection method based on the discrete Fourier transformation is proposed. The DFT phase detection method can take out frequency, phase and magnitude of the base frequency signal from a random synchronization signal. The math model and parameter design method are also proposed. Simulations and experiments validate its feasibility.