TY - GEN
T1 - In-package spiral inductor characterization for high efficiency buck converters
AU - Yan, Chen
AU - Gan, Zhihua
AU - Salman, Emre
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - The applicability of package-embedded spiral inductors to switching buck converters is demonstrated. In the first step, the design and characterization process of package-embedded spiral inductors is investigated via comprehensive full wave electromagnetic simulations, while considering a realistic, multi-layer flip-chip package. An interleaved multi-phase buck converter with an array of package-embedded spiral inductors is developed in the second step. The converter produces an output voltage of 0.9 V from 1.2 V input voltage while supplying a load current of 1 A. The flexibility of the package is exploited to obtain a relatively high inductance, enabling a reduced switching frequency. Lower switching frequency minimizes the dynamic loss, thereby increasing the power efficiency. According to the extracted results of the overall layout, power efficiency of approximately 89% is achieved with 3% output ripple voltage.
AB - The applicability of package-embedded spiral inductors to switching buck converters is demonstrated. In the first step, the design and characterization process of package-embedded spiral inductors is investigated via comprehensive full wave electromagnetic simulations, while considering a realistic, multi-layer flip-chip package. An interleaved multi-phase buck converter with an array of package-embedded spiral inductors is developed in the second step. The converter produces an output voltage of 0.9 V from 1.2 V input voltage while supplying a load current of 1 A. The flexibility of the package is exploited to obtain a relatively high inductance, enabling a reduced switching frequency. Lower switching frequency minimizes the dynamic loss, thereby increasing the power efficiency. According to the extracted results of the overall layout, power efficiency of approximately 89% is achieved with 3% output ripple voltage.
UR - https://www.scopus.com/pages/publications/85032682548
U2 - 10.1109/ISCAS.2017.8050892
DO - 10.1109/ISCAS.2017.8050892
M3 - Conference contribution
AN - SCOPUS:85032682548
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -