Incorporating power reduction mechanism in arithmetic core design

Sangjin Hong; Shu Shin Chin

Incorporating power reduction mechanism in arithmetic core design

Sangjin Hong
, Shu Shin Chin

Electrical Engineering

Stony Brook University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging Trends in VLSI Systems Design
Editors	A. Smailagic, M. Bayoumi
Pages	249-250
Number of pages	2
State	Published - 2004
Event	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States Duration: Feb 19 2004 → Feb 20 2004

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Conference

Conference	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Country/Territory	United States
City	Lafayette, LA
Period	02/19/04 → 02/20/04

Cite this

@inproceedings{ea8fd3f1ccbb4f2f81a2287694b580c8,

title = "Incorporating power reduction mechanism in arithmetic core design",

abstract = "A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.",

author = "Sangjin Hong and Chin, \{Shu Shin\}",

year = "2004",

language = "English",

isbn = "0769520979",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design",

pages = "249--250",

editor = "A. Smailagic and M. Bayoumi",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",

note = "Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design ; Conference date: 19-02-2004 Through 20-02-2004",

}

Hong, S & Chin, SS 2004, Incorporating power reduction mechanism in arithmetic core design. in A Smailagic & M Bayoumi (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, pp. 249-250, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, Lafayette, LA, United States, 02/19/04.

Incorporating power reduction mechanism in arithmetic core design. / Hong, Sangjin; Chin, Shu Shin.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. ed. / A. Smailagic; M. Bayoumi. 2004. p. 249-250 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Incorporating power reduction mechanism in arithmetic core design

AU - Hong, Sangjin

AU - Chin, Shu Shin

PY - 2004

Y1 - 2004

N2 - A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.

AB - A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.

UR - https://www.scopus.com/pages/publications/4544360912

M3 - Conference contribution

AN - SCOPUS:4544360912

SN - 0769520979

SN - 9780769520971

T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

SP - 249

EP - 250

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI

A2 - Smailagic, A.

A2 - Bayoumi, M.

T2 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Y2 - 19 February 2004 through 20 February 2004

ER -

Incorporating power reduction mechanism in arithmetic core design

Abstract

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Conference

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