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Influence of Wire-Bonding Layout on Reliability in IGBT Module

  • Huazhong University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

The wire-bonding layouts influence the profiles of current density, ohmic loss and junction temperature. The temperature profile across IGBT chip is different when the wire-bonding layouts are different. Reasonable wire-bonding layout could reduce the maximum junction temperature (T_{\text{jmax}}) of the chip and slow down the aging process of the solder and bonding wires. The uniform wire-bonding layout is proposed in this paper to improve the packaging reliability of the power module. To analyze the influence of wire-bonding layouts on reliability, the centralized wire-bonding layout and uniform wire-bonding layout of bonding wires are compared. The results of the electro-thermal simulation show that using uniform wire-bonding layout reduces the T_{\text{jmax}} of the chip by 1~3 C. What's more, as distance between wire-bonding point and chip center increases, there is a minimum value of T_{\text{jmax}} in the uniform wire-bonding layout. The analytical model is deduced to study the phenomenon. To verify the simulation and theoretical analysis results, the IGBT modules with centralized wire-bonding layout and uniform wire-bonding layout of bonding wire are tested by power cycling tests (PCT). The experimental results show that the T_{\text{jmax}} of the module with uniform wire-bonding layout of bonding wire is 3.3 C lower than that of the module with centralized wire-bonding layout. Correspondingly, with the help of LESIT lifetime model, the calculated lifetime of the IGBT module with uniform wire-bonding layout increases by 1/3, compared with centralized wire-bonding layout.

Original languageEnglish
Title of host publication2020 22nd European Conference on Power Electronics and Applications, EPE 2020 ECCE Europe
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9789075815368
DOIs
StatePublished - Sep 2020
Event22nd European Conference on Power Electronics and Applications, EPE 2020 ECCE Europe - Lyon, France
Duration: Sep 7 2020 → Sep 11 2020

Publication series

Name2020 22nd European Conference on Power Electronics and Applications, EPE 2020 ECCE Europe

Conference

Conference22nd European Conference on Power Electronics and Applications, EPE 2020 ECCE Europe
Country/TerritoryFrance
CityLyon
Period09/7/20 → 09/11/20

Keywords

  • Packaging
  • Power cycling
  • Power semiconductor device
  • Reliability
  • Simulation

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