TY - GEN
T1 - Integrated CMOS imager for pattern recognition
AU - Sarje, Anshu
AU - Satsangi, Sharad
AU - Skipwith, Armstard C.
AU - Chiang, Jui Ping
AU - Abshire, Pamela
PY - 2008
Y1 - 2008
N2 - This paper presents an analog CMOS architecture for on-chip pattern recognition. The system comprises a CMOS imager in the front end followed by low power computation circuitry for determining a match between the captured image and image patterns stored in on-chip memory. The imager has a programmable kernel selector and correlated double sampling circuit for suppression of fixed pattern noise. The closeness of a successful match can be controlled by an input bias current. The prototype with a 6×6 pixel array in a 0.5 μm CMOS process is being implemented. This chip can be used for applications requiring dedicated pattern recognition.
AB - This paper presents an analog CMOS architecture for on-chip pattern recognition. The system comprises a CMOS imager in the front end followed by low power computation circuitry for determining a match between the captured image and image patterns stored in on-chip memory. The imager has a programmable kernel selector and correlated double sampling circuit for suppression of fixed pattern noise. The closeness of a successful match can be controlled by an input bias current. The prototype with a 6×6 pixel array in a 0.5 μm CMOS process is being implemented. This chip can be used for applications requiring dedicated pattern recognition.
UR - https://www.scopus.com/pages/publications/63649143913
U2 - 10.1109/BIOCAS.2008.4696913
DO - 10.1109/BIOCAS.2008.4696913
M3 - Conference contribution
AN - SCOPUS:63649143913
SN - 9781424428793
T3 - 2008 IEEE-BIOCAS Biomedical Circuits and Systems Conference, BIOCAS 2008
SP - 217
EP - 220
BT - 2008 IEEE-BIOCAS Biomedical Circuits and Systems Conference, BIOCAS 2008
T2 - 2008 IEEE-BIOCAS Biomedical Circuits and Systems Conference, BIOCAS 2008
Y2 - 20 November 2008 through 22 November 2008
ER -