TY - GEN
T1 - Leveraging ReRAM Crossbar for Octave Convolution in Deep Neural Networks
AU - Abdurrob, Abrar
AU - Salman, Emre
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - This paper proposes a co-design method that integrates the central processing unit (CPU) and resistive random-access memory (ReRAM) crossbar to enhance energy efficiency of Octave convolution. In this method, low-frequency operations within the Octave framework are executed by the energy-efficient ReRAM crossbar, while high-frequency computations, which are crucial for accuracy, are processed by the CPU and results are combined within the CPU to finalize the classification task. Compared to vanilla convolution, for ResNet-50 trained on the CIFAR-10 dataset, this approach reduces the number of CPU operations by 37% while improving accuracy by 4.7%. Compared to traditional Octave convolution, the proposed approach reduces the number of CPU operations by 17% while maintaining accuracy within 2%. Approximately 18.5% of the total operations is executed by the energy-efficient ReRAM in the proposed approach.
AB - This paper proposes a co-design method that integrates the central processing unit (CPU) and resistive random-access memory (ReRAM) crossbar to enhance energy efficiency of Octave convolution. In this method, low-frequency operations within the Octave framework are executed by the energy-efficient ReRAM crossbar, while high-frequency computations, which are crucial for accuracy, are processed by the CPU and results are combined within the CPU to finalize the classification task. Compared to vanilla convolution, for ResNet-50 trained on the CIFAR-10 dataset, this approach reduces the number of CPU operations by 37% while improving accuracy by 4.7%. Compared to traditional Octave convolution, the proposed approach reduces the number of CPU operations by 17% while maintaining accuracy within 2%. Approximately 18.5% of the total operations is executed by the energy-efficient ReRAM in the proposed approach.
UR - https://www.scopus.com/pages/publications/105010611955
U2 - 10.1109/ISCAS56072.2025.11043525
DO - 10.1109/ISCAS56072.2025.11043525
M3 - Conference contribution
AN - SCOPUS:105010611955
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Y2 - 25 May 2025 through 28 May 2025
ER -