Low power parallel multiplier design for DSP applications through coefficient optimization

Sangjin Hong; Suhwan Kim; Marios C. Papaefthymiou; Wayne E. Stark

doi:10.1109/ASIC.1999.806521

Low power parallel multiplier design for DSP applications through coefficient optimization

Sangjin Hong
, Suhwan Kim
, Marios C. Papaefthymiou
, Wayne E. Stark

Electrical Engineering

University of Michigan, Ann Arbor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

52 Scopus citations

Abstract

Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers.

Original language	English
Title of host publication	Proceedings - 12th Annual IEEE International ASIC/SOC Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	286-290
Number of pages	5
ISBN (Electronic)	0780356322, 9780780356320
DOIs	https://doi.org/10.1109/ASIC.1999.806521
State	Published - 1999
Event	12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: Sep 15 1999 → Sep 18 1999

Publication series

Name	Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Conference

Conference	12th Annual IEEE International ASIC/SOC Conference
Country/Territory	United States
City	Washington
Period	09/15/99 → 09/18/99

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10.1109/ASIC.1999.806521

Cite this

Hong, S., Kim, S., Papaefthymiou, M. C., & Stark, W. E. (1999). Low power parallel multiplier design for DSP applications through coefficient optimization. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 286-290). Article 806521 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806521

@inproceedings{c455a9091a1148a3b18d38406e6252a9,

title = "Low power parallel multiplier design for DSP applications through coefficient optimization",

abstract = "Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers.",

author = "Sangjin Hong and Suhwan Kim and Papaefthymiou, \{Marios C.\} and Stark, \{Wayne E.\}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",

year = "1999",

doi = "10.1109/ASIC.1999.806521",

language = "English",

series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "286--290",

booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

}

Hong, S, Kim, S, Papaefthymiou, MC & Stark, WE 1999, Low power parallel multiplier design for DSP applications through coefficient optimization. in Proceedings - 12th Annual IEEE International ASIC/SOC Conference., 806521, Proceedings - 12th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers Inc., pp. 286-290, 12th Annual IEEE International ASIC/SOC Conference, Washington, United States, 09/15/99. https://doi.org/10.1109/ASIC.1999.806521

Low power parallel multiplier design for DSP applications through coefficient optimization. / Hong, Sangjin; Kim, Suhwan; Papaefthymiou, Marios C. et al.
Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 286-290 806521 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hong, Sangjin

AU - Kim, Suhwan

AU - Papaefthymiou, Marios C.

AU - Stark, Wayne E.

PY - 1999

Y1 - 1999

N2 - Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers.

AB - Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a collection of smaller multiplications with shorter critical paths. Significant energy savings are achieved by performing these multiplications in parallel with a scaled supply voltage. Dissipation is further reduced by disabling the multiplier rows that do not affect the multiplication's outcome. We have used our methodology to design a low-power parallel multiplier for the Fast Fourier Transform. Simulation results show that our approach can result in significant power savings over conventional multipliers.

UR - https://www.scopus.com/pages/publications/84935000961

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DO - 10.1109/ASIC.1999.806521

M3 - Conference contribution

AN - SCOPUS:84935000961

T3 - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

SP - 286

EP - 290

BT - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th Annual IEEE International ASIC/SOC Conference

Y2 - 15 September 1999 through 18 September 1999

ER -

Hong S, Kim S, Papaefthymiou MC, Stark WE. Low power parallel multiplier design for DSP applications through coefficient optimization. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc. 1999. p. 286-290. 806521. (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). doi: 10.1109/ASIC.1999.806521

Low power parallel multiplier design for DSP applications through coefficient optimization

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